1. Field of the Invention
The invention relates to memory circuits, particularly to RAM (random access memory) circuits, with memory redundancy for the substitution of defect memory cells.
2. Description of the Related Art
RAM circuits comprise one or more two-dimensional arrays of 1-bit-memory cells. In DRAM (dynamic random access memory) circuits the information storage in a memory cell is based on the charge state of a capacitor, whereas in SRAM (static random access memory) circuits flip-flops with positive feedback for information storage are employed.
The memory cells of one array are arranged into y rows and x columns. The memory cells of one row are assigned to one wordline, whereas the memory cells of one column are assigned to one bitline. The memory cells are selected via the signals on the wordlines; for the actual data access, i.e. reading and writing of the data, the bitlines are employed.
Generally, RAM circuits are accessed word-oriented via an appropriate address signal, i.e. each code of the address signal is assigned to a specific number of n memory cells within one memory array which are read out or written in parallel. The n-bit-wide information is equivalent to one word. Consequently, such RAM circuits comprise n-bit-wide inputs and outputs with n ports. In this case, to each port of the n ports a plurality of x/n bitlines is assigned, with one bitline per port being selectable via port-related column multiplexers.
For word-oriented memory access a multi-bit-wide address signal is applied to the RAM circuit, which generally exhibits three code components. A first code component, typically Id(y)-bit-wide, specifies the wordline of the accessed memory cells. A second code component, typically Id(x/n)-bit-wide, specifies one bitline for each plurality of x/n grouped bitlines. The optional third code component specifies the index of the memory array in case more than one memory array is employed.
RAM circuits may contain one or more randomly distributed defective memory cells after fabrication. Without appropriate countermeasures such RAM circuits with defect memory cells would be unusable for most applications even if only a small number of memory cells compared to the total number is affected. Generally, the larger the number of memory cells within one memory array, the lower the probability that the array is fault-free.
To prevent most RAM memories from being discarded once one or more defect memory cells are located during memory test, substitution memory cells are provided which allow a substitution of such defective memory cells within the main memory. Normally, the address codes or subsets thereof of the substituted memory cells are stored in non-volatile memory cells, which are generally implemented by fuses. If a memory cell is accessed the stored address information is compared with the actual address information of the address signal. In case of a positive comparison result the access is redirected to the substitution memory cells.
For the substitution of defect memory cells, different approaches are conceivable.
1. Bitline-related Repair Approach
According to the so called bitline-related repair approach a complete bitline-related set of y memory cells being connected to the same bitline in one memory array is substituted with y substitution memory cells. In case a substituted bitline-related set comprises y=512 memory cells, all 512 memory cells are substituted.
2. Wordline-related Repair Approach
In case a wordline-related repair approach is employed, a complete word-line-related set of x memory cells being connected to the same wordline in one memory array is substituted by the same number of substitution memory cells. Similar to the bitline-related repair approach all memory cells connected to one wordline (e.g. 512 memory cells) are substituted.
3. Word-related Repair Approach
By applying a word-related repair approach, a word-related set of n memory cells which are addressed by one single address code is substituted by the same number of substitution memory cells.
4. Port-related or I/O-related Repair Approach
The port-related repair approach (also called I/O repair) is an extension of the bitline-related repair approach, i.e. more than one bitline is substituted. According to a port-related repair approach those x/n*y memory cells which are connected to a plurality of x/n bitlines, with the x/n bitlines being assigned to one port, i.e. connected to one column multiplexer, are substituted by the same number of substitution memory cells.
Generally, the bitline-related repair approach and the wordline-related repair approach are alternatively employed.
Regarding the implementation of the bitline-related repair approach or alternatively the wordline-related repair approach, additional bitlines or additional wordlines, respectively, which are connected to substitution memory cells are provided. Thus, the main memory and the substitution memory form a common array of main memory cells and substitution memory cells.
Consequently, the memory cells of the main memory and the substitution memory are typically identical. Thus, process failures affecting the yield of the memory cells of the main memory affect the yield of the substitution memory cells in the same way.
A further drawback of such an implementation of the bitline-related repair approach or alternatively the wordline-related repair is that the memory access time of the RAM circuit is increased in comparison to the memory access time of a RAM circuit without bitline-related or wordline-related substitution memory. This is due to the fact that earlier to the actual memory access the above-mentioned comparison regarding stored address information is performed.
In case the RAM circuit comprises more than one memory array, additional bitlines or wordlines which are connected to substitution memory cells, appropriate comparators and fuses for non-volatile address information storage are needed for each memory array. This leads to a large area over-head.
In addition, the concrete implementation of the bitline-related or wordline-related repair approach is only valid for a particular implementation of the main memory.
The document U.S. Pat. No. 6,484,271 B1 describes a memory system with redundancy for the substitution of defective memory cells within a main memory. The main memory comprises a plurality of memory instances. An extra substitution or redundant memory is provided which substitutes defective memory cells within the main memory, with the substitution memory being capable to substitute word-related sets of memory cells. The substitution memory is not capable to substitute complete wordline-related sets of memory cells or bitline-related sets of memory cells.
In the document U.S. Pat. No. 5,644,541 a memory system with redundancy for the substitution of defective memory cells within a plurality of DRAM memory circuits is presented. Similar to the document U.S. Pat. No. 6,484,271 B1 an extra substitution memory is provided, which substitutes defective memory cells within the plurality of DRAM memory circuits. The substitution memory substitutes single defective memory cells within the plurality of DRAM memory circuits. Complete wordline-related or bitline-related sets of memory cells within the plurality of DRAM memory circuits are not substi-tuted.